The week's pick
Reseach Article
Analysis of Power Efficient Modulo 2n+1 Adder Architectures
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 70 - Number 4 |
| Year of Publication: 2013 |
| Authors: M.parimaladevi, R.karthi |
10.5120/11948-7765
|
M.parimaladevi, R.karthi . Analysis of Power Efficient Modulo 2n+1 Adder Architectures. International Journal of Computer Applications. 70, 4 ( May 2013), 8-16. DOI=10.5120/11948-7765
Abstract
Two modified architectures for modulo 2n+1 adders are introduced in this paper. Only some of the carries of modulo 2n+1 addition are computed in sparse carry computation unit present in first architecture. This sparse approach is introduced by inverted circular idempotency property of the parallel-prefix carry operator and in this modified pre-processing stage and carry select blocks are combine the multiplexer operation of a diminished-one adder can be implemented in smaller LUT's and less consumes power, while maintain the same operating speed and delay. The modulo adder 2n+1 adders can be easily derived by adding extra logic of modulo 2n-1 adders present in second architecture.
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